1. Field of the Invention
This invention relates to a digital signal processor and a processor, and more particularly to a digital signal processor and a processor improved toward a decrease of processing instructions during execution of conditional instructions.
2. Description of the Prior Art
Processing by a digital signal processor (hereinafter called DSP) is pipeline-controlled, and it is divided into three steps, namely, fetching of an instruction, decoding of the instruction and execution of the instruction for instance. An example of pipeline processing made up of these three steps is shown in FIG. 4.
As shown in FIG. 4, in pipeline processing of DSP, fetching, decoding and execution of an instruction progress in parallel. That is, when fetching of an instruction N is completed, the instruction N is decoded, and a next instruction N+1 is fetched concurrently. Then, the instruction N is executed, instruction N+1 is decoded, and a still next instruction N+2 is fetched. In this manner, by dividing processing of every single instruction into three steps, processing of instructions is repeated sequentially.
For executing such pipeline processing, it was the problem that one cycle had to be skipped before a condition execution instruction. That is, an instruction other than xe2x80x9ccondition generation instruction or condition execution instructionxe2x80x9d had to be inserted before the condition execution instruction. In other words, an instruction not changing the condition flag and other than the condition execution instruction had to be inserted. Grounds of this problem is explained below in detail with reference to FIGS. 5 through 7.
FIG. 5 is a diagram showing a hardware construction of DSP for transferring contents of a register A to a register B under a condition by using such a pipeline processing function. FIG. 6 is a timing chart in case of the condition being consistent. FIG. 7 is a timing chart in case of the condition being inconsistent.
As shown in FIG. 5, a program counter is supplied to instruction memory 100. Based on a value of the program counter, an instruction is read and introduced into an instruction register 102 in an instruction fetch cycle. The instruction taken into the instruction register 102 is decoded by an instruction decoder 104 in an instruction decode cycle. The instruction decoder 104 is supplied with a condition flag Z from a condition judge block 106. The instruction decoder 104 decodes the condition flag Z as well upon decoding the instruction from the instruction register 102. Therefore, the content of the condition flag Z has to be fixed before decoding the instruction. In accordance with the content of the condition flag Z, that is, depending on whether the condition is consistent or not, a signal is output to a gate 108 of the register A. That is, when the condition is consistent, an enable signal is output to the gate 108. When the condition is not consistent, the enable signal is not output to the gate 108. Therefore, when the condition is inconsistent, the value of the register A does not ride on the data bus. When the condition is consistent, a B register clock is supplied to a register B from an OR circuit 110, and the content of the register A is taken into the register B. In contrast, when the condition is inconsistent, no B register clock signal is supplied to the B register from the OR circuit 110, and the content of the register A is not taken into the register B.
Next explained is an operation timing in case of consistency of the condition with reference to FIG. 6. Instruction N is an instruction for generating a condition, with which the flag Z becomes 1 or 0 in accordance with the result of an operation instruction, for example. Instruction N+1 is an instruction other than xe2x80x9ccondition generation instruction or condition execution instructionxe2x80x9d, which does not change the flag Z and which is other than condition execution instruction. Typically, xe2x80x9cNo Operationxe2x80x9d instruction which instructs nothing be executed is inserted. Instruction N+2 is a condition execution instruction which instructs execution of the instruction only under a certain result of the instruction N. For example, it is such as xe2x80x9cif Z=0 then B=Axe2x80x9d.
As will be understood from FIG. 6, instruction N for generating a condition is fetched in a clock cycle T1. In the next clock cycle T2, instruction N is decoded, and instruction N+1 other than xe2x80x9ccondition generation instruction or condition execution instructionxe2x80x9d is fetched simultaneously. In the next clock cycle T3, instruction N is executed, and the condition flag Z rises upon the rising edge of the register clock. In the clock cycle T3, instruction N+1 is decoded simultaneously. However, since the condition flag Z does not rise during decoding, the proper content is not obtained yet even by decoding the condition execution instruction. Therefore, instruction N+1 other than xe2x80x9ccondition generation instruction or condition execution instructionxe2x80x9d has to be inserted. In the clock cycle T3, instruction N+2 which is condition execution instruction is fetched concurrently.
In the clock cycle T4, instruction N+2 is decoded. In the clock cycle T4, since execution of the instruction N for generating a condition is already completed, the condition flag Z is up. Therefore, condition execution instruction N+2 meets with the condition flag Z, proper decoding is executed. That is, in the example of FIG. 6 on a case with the condition being consistent, decoding is executed to replace the register B with the register A. As a result, the value of the register A rides on the data bus at the rising edge of the register clock, and the B register clock enable changes from HIGH to LOW.
In the clock cycle T5, condition execution instruction N+2 is executed. That is, the B register clock is input to the register B, and the value on the data bus is taken into the B register at the rising edge of the B register clock. In the next clock cycle T6, et seq., the value of the register B maintains the value of the register A taken last.
Next explained is an operation timing of a case where the condition is inconsistent. As shown in FIG. 7, the sequence progresses in the same manner as the case with the condition being consistent up to the clock cycle T3. Therefore, also in the clock cycle T4, et seq., the condition flag Z keeps down. B register clock enable keeps HIGH. As a result, no B register clock is supplied to the B register.
In the clock cycle T4, condition execution instruction N+2 is decoded. During the decoding process, the condition flag Z is decoded together. In this case, since the condition is inconsistent, it is necessary to prevent replacement of the register B by the content of the register A. For this purpose, condition execution instruction is changed to xe2x80x9cNo Operationxe2x80x9d instruction upon decoding. Therefore, the content of the register A does not ride on the data bus in the clock cycle T5. Additionally, since no B register clock is input to the B register, the content of the register B is not changed. Also in the clock cycle T6, the content of the register B is not changed.
As explained above, conventional techniques involved the constraint that one cycle had to be skipped before a condition execution instruction. That is, since it was necessary to complete execution of a condition generation instruction and fix the content of the condition flag Z upon decoding a condition execution instruction, there was the constraint that an instruction other than xe2x80x9ccondition generation instruction or condition execution instructionxe2x80x9d had to be inserted between an instruction for generating a condition and a condition execution instruction. The requirement to insert a redundant instruction which is an instruction other than xe2x80x9ccondition generation instruction or condition execution instructionxe2x80x9d was one of factors increasing useless processes. Especially when a program containing such instructions had to be repeatedly executed as a loop over thousands or ten thousands of times, this problem greatly affected the entire processing time and could not be disregarded.
It is therefore an object of the invention to provide a digital signal processor and a processor which need not skip one cycle just before a condition execution instruction, if any. That is, it is intended with the present invention to provide a digital signal processor and a processor not requiring insertion of an instruction other than xe2x80x9ccondition generation instruction or condition execution instructionxe2x80x9d between an instruction for generating a condition and a condition execution instruction. In other words, the invention has its object in providing a digital signal processor and a processor capable of consecutively executing an instruction for generating a condition and a condition execution instruction using the condition. Additionally, the invention intends to provide a digital signal processor and a processor removing the need for inserting an instruction other than xe2x80x9ccondition generation instruction or condition execution instructionxe2x80x9d in this manner and thereby improving the efficiency of the entire processing.
According to the invention, there is provided a digital signal processor for executing pipeline processing divided into at least three steps which are an instruction fetch cycle, an instruction decode cycle and an instruction execution cycle, comprising:
instruction memory storing a program;
an instruction register synchronous with a first clock signal to fetch an instruction of the program from the instruction memory in accordance with a program counter in the instruction fetch cycle;
an instruction decoder synchronous with the fist clock signal to decode the instruction fetched in the instruction register in the instruction decode cycle, the instruction decoder decoding the instruction under the assumption that a condition be consistent when the instruction is a condition execution instruction whose execution depends upon a result of execution of an instruction for generating the condition; and
a conditional instruction execution circuit synchronous with the first clock signal to execute the instruction pursuant to a result of decoding and store a result of execution in the instruction execution cycle, the conditional instruction execution circuit being configured to execute the condition execution instruction and store the result of execution of the condition execution instruction in the instruction execution cycle for the condition execution instruction when the condition is consistent as a result of execution of the instruction for generating the condition, and to execute the condition execution instruction but not store the result of execution of the condition execution instruction when the condition is inconsistent.
According to the invention, there is further provided a digital signal processor for executing pipeline processing divided into at least three steps which are an instruction fetch cycle, an instruction decode cycle and an instruction execution cycle, comprising:
instruction memory storing a program;
an instruction register synchronous with a first clock signal to fetch an instruction of the program from the instruction memory in accordance with a program counter in the instruction fetch cycle;
an instruction decoder synchronous with the fist clock signal to decode the instruction fetched in the instruction register in the instruction decode cycle, the instruction decoder outputting a first enable signal to one register so as to put the value of the one register onto a data bus under the assumption that a condition be consistent in the case where the decoded instruction is a condition execution instruction for transferring the value of the one register to another register only when the result of execution of the instruction for generating a condition is consistent with a predetermined condition; and
a gating circuit for controlling the supply of a second clock signal in the instruction execution cycle of the condition execution instruction to supply said second clock signal to the another register thereby to permit same to introduce the value on the data bus upon consistency of the condition, and not to supply the second clock signal to the another register thereby to prevent the value on the data bus from being introduced into the another register upon inconsistency of the condition.
According to the invention, there is further provided a processor for executing pipeline processing divided into at least three steps which are an instruction fetch cycle, an instruction decode cycle and an instruction execution cycle, comprising:
instruction memory storing a program;
an instruction register synchronous with a first clock signal to fetch an instruction of the program from the instruction memory in accordance with a program counter in the instruction fetch cycle;
an instruction decoder synchronous with the fist clock signal to decode the instruction fetched in the instruction register in the instruction decode cycle, the instruction decoder decoding the instruction under the assumption that a condition be consistent when the instruction is a condition execution instruction whose execution depends upon a result of execution of an instruction for generating the condition; and
a conditional instruction execution circuit synchronous with the first clock signal to execute the instruction pursuant to a result of decoding and store a result of execution in the instruction execution cycle, the conditional instruction execution circuit being configured to execute the condition execution instruction and store the result of execution of the condition execution instruction in the instruction execution cycle for the condition execution instruction when the condition is consistent as a result of execution of the instruction for generating the condition, and to execute the condition execution instruction but not store the result of execution of the condition execution instruction when the condition is inconsistent.